1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device with a capacitor.
2. Description of the Background Art
In recent years, a cylindrical capacitor structure wherein the effective area of an actual capacitor can be made large relative to the projection area of the memory cell has been widely used while, at the same time, miniaturization of the structure of semiconductor devices, in particular of DRAMs (dynamic random access memories), has proceeded. Such a cylindrical capacitor structure has a layered structure provided with a lower electrode formed in a cylinder, a dielectric film covering the surface of the lower electrode and a cell plate. FIG. 54 is a cross sectional view showing a semiconductor device having a cylindrical capacitor structure according to prior art.
With reference to FIG. 54, gate electrodes 104a to 104c are formed above the main surface 101a of a semiconductor substrate 101 with gate insulating films 103a to 103c intervened there between. Impurity regions 102a to 102d, as source/drain regions having a predetermined depth, are formed in main surface 101a of semiconductor substrate 101 so as to be located on both side faces of gate electrodes 104a to 104c. An impurity region 102e, having a predetermined depth, is formed at a distance away from impurity region 102d in main surface 101a of semiconductor substrate 101. Sidewall insulating films 115a to 105c are formed on the sidewalls of gate electrodes 104a to 104c. Coating insulating films 106a to 106c are formed on the top faces of gate electrodes 104a to 104c. 
A first interlayer insulating film 107 made of a silicon oxide film is formed so as to cover main surface 101a of semiconductor substrate 101, coating insulating films 106a to 106c and sidewall insulating films 105a to 105c. Contact holes 108a and 108b, reaching impurity regions 102b and 102c are formed in first interlayer insulating film 107. Conductor films 109a and 109b are filled into contact holes 108a and 108b. 
A second interlayer insulating film 110 made of a silicon oxide film is formed on first insulating film 107. A contact hole 111a reaching the top face of conductor film 109b is formed in second interlayer insulating film 110. A contact hole 111b reaching to impurity region 102e formed in main surface 101a of semiconductor substrate 101 is formed in first and second interlayer insulating films 107 and 110. Conductor films 115a and 115b are filled into contact holes 111a and 111b. First wire films 112a and 112b are formed on the top face of second interlayer insulating film 110 so as to make contact with conductor films 115a and 115b. 
A third interlayer insulating film 113 made of a silicon oxide film is formed so as to cover second interlayer insulating film 110, first wire films 112a and 112b. A contact hole 114 reaching conductor film 109a formed in first interlayer insulating film 107 is formed in second and third interlayer insulating films 110 and 113. A conductor film 116 is filled into contact hole 114.
A fourth interlayer insulating film 118 made of a silicon oxide film is formed on third interlayer insulating film 113. A hole 119 reaching conductor film 116 formed in third interlayer insulating film 113 is formed in fourth interlayer insulating film 118. A cylindrical lower storage node electrode 120 is formed so as to cover the side face and the bottom face of hole 119 wherein lower storage node electrode 120 makes contact with conductor film 116. A dielectric film 121 is formed so as to cover the surface of lower storage node electrode 120 and a portion of the top face of fourth interlayer insulating film 118. An upper cell plate electrode 122 is formed so as to cover dielectric film 121 and so as to completely fill in the inside of hole 119. Lower storage node electrode 120, dielectric film 121 and upper cell plate electrode 122 form a cylindrical capacitor in a semiconductor device.
A fifth interlayer insulating film 123 made of a silicon oxide film is formed so as to cover upper cell plate electrode 122 and fourth interlayer insulating film 118. A contact hole 152a penetrating through upper cell plate electrode 122 and dielectric film 121 so as to reach the inside of fourth interlayer insulating film 118 is formed in fifth interlayer insulating film 123. The bottom face of contact hole 152a is defined by fourth interlayer insulating film 118. A contact hole 152b reaching first wire film 112b formed on the top face of second interlayer insulating film 110 is formed in third, fourth and fifth interlayer insulating films 113, 118 and 123. Conductor films 153a and 153b are filled into contact holes 152a and 152b. Conductor film 153a is connected to the sidewall of upper cell plate electrode 122 resulting from the formation of contact hole 152a. Second wire films 154a and 154b are formed on the top face of fifth interlayer insulating film 123 so as to make contact with conductor films 153a and 153b. 
In a semiconductor device having such a cylindrical capacitor, it is necessary to increase the height of the capacitor in order to maintain the capacitance of the capacitor while reducing the size of the memory cell. Therefore, the height of fourth interlayer insulating film 118 tends to increase and the distance between the top face of fifth interlayer insulating film 123 and first wire film 112b becomes greater due, in particular, to this tendency.
In addition, for the purpose of setting upper cell plate electrode 122 at a predetermined potential, second wire film 154a provided on fifth interlayer insulating film 123 and upper cell plate electrode 122 are connected by conductor film 153a. Therefore, it is necessary to form contact hole 152a into which conductor film 153 is filled. On the other hand, for the purpose of supplying a signal to impurity region 102e and for fixing the potential thereof, second wire film 154b provided on fifth interlayer insulating film 123 and first wire film 112b provided on second interlayer insulating film 110 are connected by conductor film 153b. Therefore, it is necessary to form contact hole 152b into which conductor film 153b is filled.
These contact holes 152a and 152b are formed in the same etching step, after the provision of fifth interlayer insulating film 123, in order to reduce the number of manufacturing steps. Then, this etching step is carried out until contact hole 152b reaches first wire film 112b. Therefore, contact hole 152a first reaches the top face of upper cell plate electrode 122 and, after that, upper cell plate electrode 122 continuously undergoes etching until contact hole 152b reaches first wire film 112b. As a result of this, as shown in FIG. 54, a formation is obtained wherein contact hole 152a penetrates through upper cell plate electrode 122 so as to reach the inside of fourth interlayer insulating film 118.
In the case that contact hole 152a penetrates through upper cell plate electrode 122 in such a manner, and the amount of penetration is great, a problem arises wherein conductor film 153a is short circuited to, for example, first wire film 112a. 
In addition, the area of contact between conductor film 153a filled into contact hole 152a and upper cell plate electrode 122 is only the sidewall of upper cell plate electrode 122 resulting from the formation of contact hole 152a and, therefore, the area of contact is small. In addition, in the case that conductor film 153a is formed by means of sputtering, the coverage of film formation is insufficient on the sidewall of upper cell plate electrode 122. Furthermore, in the case that the sidewall of upper cell plate electrode 122 recedes as a result of a wet process after the formation of contact hole 152a, the coverage of conductor film 153a at the time of film formation is worsened. Because of the above reasons, there is a risk that a defective contact between upper cell plate electrode 122 and conductor film 153a may generate.
Japanese Patent Laying-Open No. 2000-216357, for example, discloses a semiconductor device wherein a defective contact with a cell plate is prevented from generating for the purpose of solving the above problem. FIG. 55 is a cross sectional view showing the semiconductor device disclosed in Japanese Patent Laying-Open No. 2000-216357.
With reference to FIG. 55, gate electrodes 204 are formed above a silicon substrate 201 having an element isolation oxide film 202 and diffusion layer regions 203 with gate insulating films intervened there between. Nitrided films 205 are formed on the top faces of gate electrodes 204 and sidewall oxide films 206 are formed on the sidewalls of gate electrodes 204. A first interlayer insulating film 216 is formed so as to cover gate electrodes 204 and the main surface of silicon substrate 201. Local wires 207 reaching to diffusion layer regions 203 are formed in first interlayer insulating film 216. A second interlayer insulating film 217 is formed on first interlayer insulating film 216. A storage electrode 208 having a cylindrical structure is formed in second interlayer insulating film 217. Storage electrode 208 is electrically connected to a diffusion layer region 203 via a local wire 207.
A capacitance electrode 210 made of polysilicon is formed above storage electrode 208 with a capacitance insulating film intervened there between. A third interlayer insulating film 218 covering capacitance electrode 210 is formed on second interlayer insulating film 217. Metal wires 212 are formed on third interlayer insulating film 218. Gate electrodes 204, diffusion layer regions 203 and capacitance electrode 210, respectively, are electrically connected to metal wires 212 via metal contacts 211. A contact stopper 209 formed in the same layer as storage electrode 208 is formed beneath the contact between metal contact 211 and capacitance electrode 210. The film of capacitance electrode 210 positioned beneath metal contact 211 is formed to have a great thickness due to the existence of contact stopper 209.
In the case that a contact hole reaching a gate electrode 204 and a contact hole reaching capacitance electrode 210 are simultaneously formed, the contact hole reaching capacitance electrode 210 does not penetrate through capacitance electrode 210 because capacitance electrode 210 is deposited inside of contact stopper 209. Thereby, a metal wire 212 and capacitance electrode 210 can make sufficient electrical contact.
In the above described semiconductor device shown in FIG. 55, the film of capacitance electrode 210 positioned below metal contact 211 is formed to have a great thickness in order to prevent the contact hole reaching to capacitance electrode 210 from penetrating through capacitance electrode 210. In order to implement a semiconductor device having such a structure, however, a region must be obtained having a predetermined width in which the film of capacitance electrode 210 has a great thickness above silicon substrate 201, thereby an area penalty generates. The term area penalty indicates a disadvantage caused by usage of space above a semiconductor substrate wherein a structure is provided in order to achieve a specific purpose. Therefore, a problem arises wherein the area of the memory cell region increases, so that miniaturization of the semiconductor device cannot be implemented.
In addition, in the case that the contact hole reaching capacitance electrode 210 is formed up to the vicinity of contact stopper 209, the area of the sidewall of capacitance electrode 210 that makes contact with metal contact 211 is significantly increased by the amount of thickness of the film of capacitance electrode 210. The sidewall of capacitance electrode 210 resulting from the formation of the contact hole does not have the desired surface formation due to a variety of factors at the time of etching. Therefore, a problem arises wherein the contact resistance between metal contact 211 and capacitance electrode 210 is dispersed.
Therefore, an object of the present invention is to solve the above described problem and to provide a semiconductor device wherein contact defects in the upper electrode are prevented and the generation of an area penalty is prevented.
A semiconductor device according to the present invention includes: a lower electrode provided on a main surface of a semiconductor substrate; a dielectric film provided on the lower electrode; an upper electrode provided on the dielectric film; and an interlayer insulating film covering the upper electrode. The upper electrode contains at least one type selected from the group consisting of ruthenium, titanium nitride and platinum. The interlayer insulating film has a first hole reaching the upper electrode. The first hole is provided so that the distance between the main surface of the semiconductor substrate and the bottom face of the first hole is not less than the distance between the main surface of the semiconductor substrate and the bottom face of the upper electrode in the portion where the first hole reaches.
According to a semiconductor device having such a configuration, the upper electrode contains at least one type selected from the group consisting of ruthenium, titanium nitride and platinum, which are strongly resistant to oxidation. Therefore, even in the case that the upper electrode is exposed to an atmosphere that promotes oxidation in a manufacturing step of the semiconductor device, the upper electrode can be prevented from undergoing oxidation. Therefore, the generation of contact defects due to oxidation of the upper electrode can be prevented. In addition, in the case of ruthenium, the oxides of ruthenium are also conductive. Therefore, even when the upper electrode undergoes oxidation, contact defects do not generate in the upper electrode.
In addition, the sidewall of the upper electrode defined by the first hole does not have a depth greater than a constant depth. Therefore, the upper electrode can be provided with a stable contact resistance between the upper electrode and the conductive film filled into the first hole. Furthermore, contact defects of the upper electrode are prevented through the formation of the upper electrode of predetermined materials, instead of relying upon the specific structure. Accordingly, no area penalty is produced so that miniaturization of the semiconductor device can be implemented.
In addition, the first hole is formed in a manner that does not allow penetration beyond the upper electrode. Therefore, there is no risk of the first hole reaching a wire film or the like, separately provided from the upper electrode so that the conductive film filled into the first hole and this wire film form a short circuit. In addition, the bottom of the first hole is defined by the upper electrode, except for the case where the distance between the main surface of the semiconductor substrate and the bottom face of the first hole is equal to the distance between the main surface of the semiconductor substrate and the bottom face of the upper electrode. Therefore, the area of contact between the conductive film filled into the first hole and the upper electrode increases so that contact defects due to small contact area can be prevented.
In addition, the semiconductor device is preferably further includes a conductive film formed within the interlayer insulating film so that the distance between the top face of the interlayer insulating film and the conductive film is greater than the distance between the top face of the interlayer insulating film and the upper electrode. The interlayer insulating film has a second hole reaching the conductive film. The predetermined etchant used to form first and second holes through the removal of portions of the interlayer insulating film etches the upper electrode at a relatively low etching rate, while the predetermined etchant etches the interlayer insulating film at a relatively high etching rate.
According to the semiconductor device having such a configuration, in the case that the interlayer insulating film is etched so that the first hole and second hole, which is deeper than the first hole, are simultaneously formed, the upper electrode continues to undergo etching after the first hole has reached the top face of the upper electrode. However, the etchant for removal of portions of the interlayer insulating film etches the upper electrode at a relatively low etching rate and, therefore, it is difficult to etch the upper electrode when the interlayer insulating film is etched. Therefore, even when the upper electrode continues to undergo etching, etching stops at a predetermined position of the upper electrode so that the first hole is formed in a manner that does not allow penetration beyond the upper electrode. Thereby, the desired contact structure between the upper electrode and the conductive film filled into the first hole can be obtained.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.